FPGAs may be used to implement large systems that include millions of gates and megabits of embedded memory. Today, FPGAs may utilize fracturable logic cells. Fracturable logic cells include a variety of look-up table (LUT)-based resources that can be used to implement a single adaptive LUT having a first number of inputs or be divided between a plurality of adaptive LUTs having the same or a different number of inputs. Each fracturable logic cell may be used to implement more than one function. Compared to traditional logic cells that may only implement a single function, fracturable logic cells provide designers with more flexibility and more opportunities to maximize the utilization of resources on FPGAs.
The process flow for implementing a system onto a target FPGA device includes performing synthesis, mapping, placement, and routing. Synthesis involves generating a logic design of the system to be implemented by a target device and mapping the logic design onto resources on the FPGA that will implement the logic design. Traditional mapping techniques map components in the logic design onto LUTs assuming that each LUT supports a fixed number of inputs. Although sufficient for traditional FPGA devices, these mapping techniques are not well suited for FPGAs implementing fracturable logic cells having adaptive LUTs that support more than a single number of inputs. By assuming that the adaptive LUTs support only a single number of inputs, these mapping techniques may create inefficient solutions by either generating too many unpackable adaptive LUTs that would waste resources or fail to fully take advantage of the functionality of the adaptive LUTs to implement functions with a higher number of inputs.
Thus what is needed is an effective method and apparatus for performing mapping onto FPGAs utilizing fracturable logic cells.